DM163006 datasheet(121/320 Pages) MICROCHIP

121 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 121

PIC18C601/801

9.8

PORTH, LATH, and TRISH

Registers

PORTH is an 8-bit wide, bi-directional I/O port. The cor-

responding data direction register is TRISH. Setting a

TRISH bit (= 1) will make the corresponding PORTH

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISH bit (= 0) will

make the corresponding PORTH pin an output (i.e., put

the contents of the output latch on the selected pin).

Read-modify-write operations on the LATH register

read and write the latched output value for PORTH.

Pins RH7:RH4 are multiplexed with analog inputs

AN18:AN11, while pins RH3:RH0 are multiplexed with

system address bus A19:A16. By default, pins

RH7:RH4 will setup as A/D inputs and pins RH3:RH0

will setup as system address bus. Register ADCON1

configures RH7:RH4 as I/O or A/D inputs. Register

MEMCON configures RH3:RH0 as I/O or system bus

pins.

EXAMPLE 9-9:

INITIALIZING PORTH

FIGURE 9-16:

RH3:RH0 PINS BLOCK

DIAGRAM IN I/O MODE

FIGURE 9-17:

RH7:RH4 PINS BLOCK

DIAGRAM

Note:

PORTH is available only on PIC18C801

devices.

Note 1: On

Power-on

Reset,

PORTH

pins

RH7:RH4 default to A/D inputs and read

as ’0’.

2: On

Power-on

Reset,

PORTH

pins

RH3:RH0 default to system bus signals.

CLRF

PORTH

; Initialize PORTH by

; clearing output

; data latches

CLRF

LATH

; Alternate method

; to clear output

; data latches

MOVLW

0Fh

;

MOVWF

ADCON1

;

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISH

; Set RH3:RH0 as inputs

; RH5:RH4 as outputs

; RH7:RH6 as inputs

Data

Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATH

PORTH

Note 1: I/O pins have diode protection to VDD and VSS.

Data

Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATH

PORTH

To A/D Converter

Note 1: I/O pins have diode protection to VDD and VSS.

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