DM163006 datasheet(186/320 Pages) MICROCHIP

186 / 320 page

PIC18C601/801

DS39541A-page 186

Advance Information

 2001 Microchip Technology Inc.

FIGURE 16-5:

ASYNCHRONOUS RECEPTION

TABLE 16-7:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

START

bit

bit7/8

bit1

bit0

bit7/8

bit0

STOP

bit

START

bit

START

bit

bit7/8

STOP

bit

RX (pin)

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG

Word 2

RCREG

STOP

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

PIR1

—

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

-000 0000

PIE1

—

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE

TMR1IE

-000 0000

IPR1

—

ADIP

RCIP

TXIP

SSPIP

CCP1IP TMR2IP

TMR1IP

-000 0000

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

RCREG

USART Receive Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

ADDEN

BRGH

TRMT

TX9D

0000 0010

SPBRG

Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

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