DM163006 datasheet(190/320 Pages) MICROCHIP

190 / 320 page

PIC18C601/801

DS39541A-page 190

Advance Information

 2001 Microchip Technology Inc.

16.4

USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master

mode, in that the shift clock is supplied externally at the

RC6/TX/CK pin (instead of being supplied internally in

Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA register).

16.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the SLEEP

mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the

TSR register and transmit.

The second word will remain in TXREG register.

Flag bit TXIF will not be set.

When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will be set.

If enable bit TXIE is set, the interrupt will wake the

chip from SLEEP. If the global interrupt is enabled,

the program will branch to the interrupt vector.

When setting up a Synchronous Slave Transmission,

follow these steps:

Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit CSRC.

Clear bits CREN and SREN.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting enable bit

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

16.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode and bit SREN, which is a "don’t care" in Slave

mode.

If receive is enabled by setting bit CREN prior to the

SLEEP

instruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector.

When setting up a Synchronous Slave Reception,

follow these steps:

Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is com-

plete. An interrupt will be generated if enable bit

RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

bit CREN.

TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on all

other

RESETS

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

PIR1

—

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

-000 0000

PIE1

—

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

-000 0000

IPR1

—

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

-000 0000

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

TXREG

USART Transmit Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

ADDEN

BRGH

TRMT

TX9D

0000 0010

SPBRG

Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.

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