DM163006 datasheet(187/320 Pages) MICROCHIP

187 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 187

PIC18C601/801

16.3

USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA register).

In addition, enable bit SPEN (RCSTA register) is set, in

order to configure the RC6/TX/CK and RC7/RX/DT I/O

pins to CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA register).

16.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the Transmit

(serial) Shift register (TSR). The shift register obtains

its data from the Read/Write Transmit Buffer register

(TXREG). The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG is empty and interrupt

bit TXIF (PIR registers) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE registers). Flag bit TXIF will be set, regardless of

the state of enable bit TXIE, and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register. While flag bit TXIF indicates the

status of the TXREG register, another bit TRMT

(TXSTA register) shows the status of the TSR register.

TRMT is a read only bit, which is set when the TSR is

empty. No interrupt logic is tied to this bit, so the user

has to poll this bit in order to determine if the TSR reg-

ister is empty. The TSR is not mapped in data memory,

so it is not available to the user.

Steps to follow when setting up a Synchronous Master

Transmission:

Initialize the SPBRG register for the appropriate

baud rate (Section 16.1).

Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

TABLE 16-8:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on all

other

RESETS

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

PIR1

—

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

-000 0000

PIE1

—

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

-000 0000

IPR1

—

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

-000 0000

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

TXREG

USART Transmit Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

ADDEN

BRGH

TRMT

TX9D

0000 0010

SPBRG

Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.

DM163006 Datasheet(PDF) 187 Page - Microchip Technology

DM163006 Datasheet(HTML) 187 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL