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DM163006 Datasheet(PDF) 189 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 189 Page - Microchip Technology |
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189 / 320 page  2001 Microchip Technology Inc. Advance Information DS39541A-page 189 PIC18C601/801 16.3.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous Master mode is selected, reception is enabled by setting either enable bit SREN (RCSTA register), or enable bit CREN (RCSTA register). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. When setting up a Synchronous Master reception, fol- low these steps: 1. Initialize the SPBRG register for the appropriate baud rate (Section 16.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -000 0000 -000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. CREN bit RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’. Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 ’0’ bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ’0’ Q1 Q2 Q3 Q4 |
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