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LPC2364 Datasheet(PDF) 48 Page - NXP Semiconductors |
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LPC2364 Datasheet(HTML) 48 Page - NXP Semiconductors |
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48 / 69 page ![]() LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7.1 — 16 October 2013 48 of 69 NXP Semiconductors LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers 11. Dynamic characteristics [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] LPC2364HBD only. [4] Bus capacitance Cb in pF, from 10 pF to 400 pF. Table 9. Dynamic characteristics Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit ARM processor clock frequency foper operating frequency CCLK; 40 C to +85 C1 - 72 MHz CCLK; > 85 C [3] 1- 60 MHz IRC; 40 C to +85 C 3.96 4 4.04 MHz IRC; > 85 C [3] 3.98 4.02 4.06 MHz External clock fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns I2C-bus pins (P0[27] and P0[28]) tf(o) output fall time VIH to VIL 20 + 0.1 C b [4] -- ns SSP interface tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 C; measured in SPI Master mode; see Figure 15 -11 - ns Fig 13. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 |
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