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LPC2364 Datasheet(PDF) 52 Page - NXP Semiconductors

Part # LPC2364
Description  Single-chip 16-bit/32-bit ocontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
PDF  69 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2364 Datasheet(HTML) 52 Page - NXP Semiconductors

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LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7.1 — 16 October 2013
52 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
12. ADC electrical characteristics
[1]
Conditions: VSSA =0V, VDDA =3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 16.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 16.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 16.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 16.
[7]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 16.
[8]
See Figure 17.
Table 14.
ADC characteristics
VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C, unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIA
analog input voltage
0
-
VDDA
V
Cia
analog input capacitance
-
-
1
pF
ED
differential linearity error
[1][2][3] --
1LSB
EL(adj)
integral non-linearity
[1][4] --
2LSB
EO
offset error
[1][5] --
3LSB
EG
gain error
[1][6] --
0.5
%
ET
absolute error
[1][7] --
4LSB
Rvsi
voltage source interface
resistance
[8] --40
k



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