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LPC2364 Datasheet(PDF) 49 Page - NXP Semiconductors

Part # LPC2364
Description  Single-chip 16-bit/32-bit ocontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
PDF  69 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2364 Datasheet(HTML) 49 Page - NXP Semiconductors

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LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7.1 — 16 October 2013
49 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
11.1 Internal oscillators
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
11.2 I/O pins
[1]
Applies to standard I/O pins and RESET pin.
11.3 USB interface
[1]
Characterized but not implemented as production test. Guaranteed by design.
Table 10.
Dynamic characteristic: internal oscillators
Tamb = 40 C to +85 C; 3.0 V VDD(3V3) 3.6 V.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator frequency
-
3.96
4.02
4.04
MHz
fi(RTC)
RTC input frequency
-
-
32.768
-
kHz
Table 11.
Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin configured as output
3.0
-
5.0
ns
tf
fall time
pin configured as output
2.5
-
5.0
ns
Table 12.
Dynamic characteristics of USB pins (full-speed) (LPC2364/66/68 only)
CL = 50 pF; Rpu = 1.5 kon D+ to VDD(3V3), unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
8.5
-
13.8
ns
tf
fall time
10 % to 90 %
7.7
-
13.7
ns
tFRFM
differential rise and fall time
matching
tr /tf
--
109
%
VCRS
output signal crossover voltage
1.3
-
2.0
V
tFEOPT
source SE0 interval of EOP
see Figure 14
160
-
175
ns
tFDEOP
source jitter for differential transition
to SE0 transition
see Figure 14
2-
+5
ns
tJR1
receiver jitter to next transition
18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
9-
+9
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
Figure 14
[1] 40
--ns
tEOPR2
EOP width at receiver
must accept as
EOP; see
Figure 14
[1] 82
--ns



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