IMX51 datasheet(49/202 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6

Freescale Semiconductor

4.6.5

DPLL Electrical Parameters

Table 48 shows the DPLL electrical parameters.

4.6.6

NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among different signals of NFC at the module level

in the different operational modes.

Timing parameters in Figure 14, Figure 15, Figure 16, Figure 17, Figure 19, and Table 50 show the default

NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing

parameters in Figure 14, Figure 15, Figure 16, Figure 18, Figure 19, and Table 50 show symmetric NFC

mode using one Flash clock cycle per one access of RE_B and WE_B.

Table 48. DPLL Electrical Parameters

Parameter

Test Conditions/Remarks

Min

Typ

Max

Unit

Reference clock frequency range1

1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 47.

—

100

MHz

Reference clock frequency range after

pre-divider

—10

—

MHz

Output clock frequency range (dpdck_2)

—

300

—

1025

MHz

Pre-division factor2

2 The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user.Therefore,

the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

—1

—

Multiplication factor integer part

—

Multiplication factor numerator3

3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be

zero.

Should be less than denominator

–67108862

—

67108862

—

Multiplication factor denominator2

—

67108863

—

Output Duty Cycle

—

48.5

51.5

Frequency lock time4

(FOL mode or non-integer MF)

4 T

dpdref is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL

mode is 398 cycles of divided reference clock when DPLL starts after full reset.

——

—

398

Tdpdref

Phase lock time

—

100

µs

Frequency jitter5 (peak value)

5 Tdck is the time period of the output clock, dpdck_2.

—

0.02

0.04

Tdck

Phase jitter (peak value)

FPL mode, integer and fractional MF

—

2.0

3.5

Power dissipation

fdck = 300 MHz @ avdd = 1.8 V,

dvdd = 1.2 V

fdck = 650 MHz @ avdd = 1.8 V,

dvdd = 1.2 V

—

0.65 (avdd)

0.92 (dvdd)

1.98 (avdd)

1.8 (dvdd)

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