IMX51 datasheet(71/202 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6

Freescale Semiconductor

Figure 36 shows the timing diagram for DDR2 SDRM write cycle. The timing parameters for this diagram

appear in Table 60.

Figure 36. DDR2 SDRAM Write Cycle Timing Diagram

1 Test conditions are: Capacitance 15 pF for DDR contacts. Recommended drive strengths: Medium for SDCLK and High for

address and controls.

2 SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal

value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK_B.

Table 60. DDR2 SDRAM Write Cycle Parameter Table

Parameter

Symbol

SDCLK = 200 MHz

Unit

Min

Max

DDR17

DQ & DQM setup time to DQS

tDS

0.81

1 - In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ

window. The minimum window width is 1.6ns (DDR17+DDR18).

- From DDR controller perspective, the timing is the same for both differential and single ended mode.

—ns

DDR18

DQ & DQM hold time to DQS

tDH

0.82

2 - In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ

window. The minimum window width is 1.6ns (DDR17+DDR18).

- From DDR controller perspective, the timing is the same for both differential and single ended mode.

—ns

DDR19

DQS falling edge to SDCLK output setup time

tDSS

1.6

—

DDR20

DQS falling edge SDCLK output hold time

tDSH

2.4

—

DDR21

DQS latching rising transitions to associated clock edges

tDQSS

-0.7

0.3

DDR22

DQS high level width

tDQSH

0.35

—

tCK

DDR23

DQS low level width

tDQSL

0.35

—

tCK

SDCLK

SDCLK_B

DQS (output)

DQ (output)

DQM (output)

Data

DDR17

DDR18

DDR21

DDR23

DDR22

DDR20

DDR19

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