IMX51 datasheet(75/202 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6

Freescale Semiconductor

4.7.1.2

CSPI Slave Mode Timing

Figure 39 depicts the timing of CSPI in Slave mode. Table 66 lists the CSPI Slave Mode timing

characteristics.

Figure 39. CSPI Slave Mode Timing Diagram

CS5

SSx Lead Time (Slave Select

setup time)

tSCS

—

CS6

SSx Lag Time (SS hold time)

tHCS

—

CS7

MOSI Propagation Delay

(CLOAD =20pF)

tPDmosi

–1

CS8

MISO Setup Time

tSmiso

5—

CS9

MISO Hold Time

tHmiso

5—

CS10

RDY to SSx Time2

tSDRY

5—

1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters”

2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

Table 66. CSPI Slave Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

SCLK Cycle Time

tclk

—

CS2

SCLK High or Low Time

tSW

—

CS4

SSx pulse width

tCSLH

—

CS5

SSx Lead Time (SS setup time)

tSCS

—

CS6

SSx Lag Time (SS hold time)

tHCS

—

CS7

MOSI Setup Time

tSmosi

5—

Table 65. CSPI Master Mode Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

CS1

CS7

CS8

CS2

CS4

CS6

CS5

CS9

SCLK

SSx

MISO

MOSI

IMX51 Datasheet(PDF) 75 Page - Freescale Semiconductor, Inc

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