IMX51 datasheet(91/202 Pages) FREESCALE

91 / 202 page

Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6

Freescale Semiconductor

4.7.8.4

IPU Display Interface Timing

The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

4.7.8.4.1

Synchronous Controls

The synchronous control is a signal that changes its value as a function either of a system or of an external

clock. This control has a permanent period and a permanent wave form.

There are special physical outputs to provide synchronous controls:

•

The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

•

The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN and so on)

calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control

starts from the local start point with predefined UP and DOWN values to calculate control’s changing

points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the

i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).

4.7.8.4.2

Asynchronous Controls

The asynchronous control is a data oriented signal that changes its a value with an output data according

to an additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

•

The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays

•

The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any else data oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals

toggling. When a DI decides to put a new asynchronous data in the bus, a

new internal start (local start point) is generated. The signals generators

calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

4.7.8.5

Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.7.8.5.1

IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

•

IPP_DISP_CLK—Clock to display

•

HSYNC—Horizontal synchronization

IMX51 Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

IMX51 Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL