AT90USB646 datasheet(189/456 Pages) ATMEL

189 / 456 page

189

7593L–AVR–09/12

AT90USB64/128

The UPEn bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is

valid until the receive buffer (UDRn) is read.

19.6.6

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver

will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

19.6.7

Flushing the receive buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag

is cleared. The following code example shows how to flush the receive buffer.

Note:

1. See “About code examples” on page 10.

19.7

Asynchronous data reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

19.7.1

Asynchronous clock recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5

on page 190 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed

mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-

cess. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of

operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no com-

munication activity).

Assembly code example

(1)

USART_Flush:

sbis

UCSRnA, RXCn

ret

r16, UDRn

rjmp

USART_Flush

C code example (1)

void

USART_Flush( void )

{

unsigned char

dummy;

while

( UCSRnA & (1<<RXCn) ) dummy = UDRn;

}

AT90USB646 Datasheet(PDF) 189 Page - ATMEL Corporation

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