AT90USB646 datasheet(310/456 Pages) ATMEL

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310

7593L–AVR–09/12

AT90USB64/128

Figure 26-2. ADC auto trigger logic.

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

26.5

Prescaling and conversion timing

Figure 26-3. ADC prescaler.

By default, the successive approximation circuitry requires an input clock frequency between

50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. Alter-

natively, setting the ADHSM bit in ADCSRB allows an increased ADC clock frequency at the

expense of higher power consumption.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

ADSC

ADIF

SOURCE 1

SOURCE n

ADTS[2:0]

CONVERSION

LOGIC

PRESCALER

START

CLK

ADC

EDGE

DETECTOR

ADATE

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

Reset

ADEN

START

AT90USB646 Datasheet(PDF) 310 Page - ATMEL Corporation

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