AD7734 datasheet(6/32 Pages) AD

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AD7734

Data Sheet

Rev. A | Page 6 of 32

TIMING SPECIFICATIONS

Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.)1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Master Clock Range

6.144

MHz

SYNC Pulsewidth

500

RESET Pulsewidth

Read Operation

CS Falling Edge to SCLK Falling Edge Setup Time

SCLK Falling Edge to Data Valid Delay

DD of 4.75 V to 5.25 V

DD of 2.7 V to 3.3 V

2, 3

CS Falling Edge to Data Valid Delay

DD of 4.75 V to 5.25 V

DD of 2.7 V to 3.3 V

SCLK High Pulsewidth

SCLK Low Pulsewidth

CS Rising Edge after SCLK Rising Edge Hold Time

Bus Relinquish Time after SCLK Rising Edge

Write Operation

CS Falling Edge to SCLK Falling Edge Setup

Data Valid to SCLK Rising Edge Setup Time

Data Valid after SCLK Rising Edge Hold Time

SCLK High Pulsewidth

SCLK Low Pulsewidth

CS Rising Edge after SCLK Rising Edge Hold Time

1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV

DD) and timed from a voltage level of

1.6 V. See Figure 2 and Figure 3.

2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the V

OL or VOH limits.

3 This specification is relevant only if CS goes low while SCLK is low.

4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

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