Data Sheet

AD7734

Rev. A | Page 17 of 32

ADC STATUS REGISTER

8 Bits, Read-Only Register, Address 04h, Default Value 00h

In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel

data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to

0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the channel

data register. Writing to the mode register resets all the bits to 0.

In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the

calibration is complete.

The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register. The RDY0

bit corresponds to Channel 0, the RDY1 bit corresponds to Channel 1, and so on.

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

–

–

–

–

RDY3

RDY2

RDY1

RDY0

Default

0

0

0

0

0

0

0

0

CHECKSUM REGISTER

16 Bits, Read/Write Register, Address 05h

This register is described in the AN-626 Application Note

Using the AD7732/AD7734/ AD7738/AD7739 Checksum Register.

ADC ZERO-SCALE CALIBRATION REGISTER

24 Bits, Read/Write Register, Address 06h, Default Value 800000h

The register holds the ADC zero-scale calibration coefficient.

The value in this register is used in conjunction with the value

in the ADC full-scale calibration register and the corresponding

channel zero-scale and channel full-scale calibration registers to

scale digitally all channels’ conversion results. The value in this

register is updated automatically following the execution of an

ADC zero-scale self-calibration. Writing this register is

possible in the idle mode only (see the Calibration section for

more details).

ADC FULL-SCALE REGISTER

24 Bits, Read/Write Register, Address 07h, Default Value 800000h

This register holds the ADC full-scale coefficient. The user is

advised not to change the default configuration of this register.

CHANNEL DATA REGISTERS

16 Bit/24 Bit, Read-Only Registers, Address 08h–0Bh, Default

Width 16 Bits, Default Value 8000h

These registers contain the most up-to-date conversion results

corresponding to each analog input channel. The 16-bit or 24-

bit data width can be configured by setting the 24/16 bit in the

mode register. The relevant RDY bit in the channel status

register goes high when the result is updated. The RDY bit will

return low once the data register reading has begun. The RDY

pin can be configured to indicate when any channel has unread

data or waits until all enabled channels have unread data. If any

channel data register read operation is in progress when a new

result is updated, no update of the data register will occur. This

avoids having corrupted data. Reading the status registers can

be associated with reading the data registers in the dump mode.

Reading the status registers is always associated with reading

the data registers in the continuous read mode (see the Digital

Interface Description section for more details).