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APL5338 Datasheet(PDF) 1 Page - Anpec Electronics Coropration |
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APL5338 Datasheet(HTML) 1 Page - Anpec Electronics Coropration |
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1 / 19 page ![]() 2A Bus Termination Regulator Copyright © ANPEC Electronics Corp. Rev. A.5 - Aug., 2013 APL5338 www.anpec.com.tw 1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. • Sourcing and Sinking Current up to 2A • Wide Input Voltage Range: 1.2V to 3.6V • VTT and VTTREF Voltage Tracks at Half the VREF Voltage • VTT and VTTREF Voltage with ±10mV Accuracy • Excellent Load Transient Response • Stable with 10 µF Ceramic Output Capacitor • Current-Limit Protection • Thermal Shutdown Protection • Power-On-Reset Function on VCNTL • S3, S5 Input Signals for ACPI States • Small MSOP-10P and TDFN3x3-10 Packages • Lead Free and Green Devices Available (RoHS Compliant) Features Applications General Description The APL5338 linear regulator is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The APL5338 integrates two power transistors to source or sink current up to 2A. It also incorporates current-limit and thermal shutdown into a single chip. The output voltage of APL5338 tracks the voltage at VREF pin. An internal resistor divider is used to provide a half voltage of VREF for VTTREF and VTT Voltage. The VTT output voltage is only requiring 10 µF of ceramic output capacitance for stability and fast transient response. The S3 and S5 pins provide the sleep state for VTT (S3 state) and suspend state (S4/S5 state) for device when S5 and S3 are both pulled low the device provides the soft-off for VTT and VTTREF. The MSOP-10P and TDFN3x3-10 pack- age with a copper pad is available which provides excel- lent thermal impedance. Pin Configuration MSOP-10P (Top View) • DDR 2/3 Memory Termination Simplified Application Circuit VIN 2 9 S5 VTT 3 PGND 4 8 GND 7 S3 10 VCNTL VREF 1 VTTSEN 5 6 VTTREF VREF VTT VIN PGND VTTSNS VCNTL S5 GND S3 VTTREF APL5338 1 2 3 4 5 6 9 8 7 10 C IN 10 µF C OUT 10 µF C1 0.1 µF TDFN3X3-10 (Top View) VTT 3 10 VCNTL VREF 1 VIN 2 VTTSEN 5 9 S5 7 S3 8 GND PGND 4 6 VTTREF = Exposed Pad (connected to ground plane for better heat dissipation) GND |
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