APL3207 datasheet(14/19 Pages) ANPEC

14 / 19 page

Rev. A.3 - Sep., 2012

APL3207

www.anpec.com.tw

Input Capacitors

The APL3207 requires proper input capacitors to supply

surge current during stepping load transients to prevent

the input rail from dropping. The 1

µF ceramic capacitors

are recommended to place on the input supply pins (VIN

and VLDOIN) to the GND. Place the capacitors as close

as possible to the input supply pins for well operation. In

some start-up conditions, it may necessary to protect the

device against a hot plug input voltage. Adding a 6V input

zener diode between the input supply pins and the GND

clamps the input voltage peak.

Output Capacitors

Application Information

The APL3207 has two output pins, which are charger

output pin BATT and regulator 3.3V output pin LDOOUT.

The output capacitor of charger is recommended to use

2.2

µF ceramic capacitor to ensure the battery charge

stability.

The output capacitor of regulator also can use ceramic

capacitor, and its proper value is between 1

µF and 2.2µF,

ESR must above 10m

Ω. Large output capacitor values

can reduce noise and improve load-transient response,

stability, and PSRR. With X5R and X7R dielectrics, 1

µF is

sufficient at all operating temperatures.

STAT Pin

The STAT pin can be used to drive a LED or communicate

with the host processor to show the charge status. When

the status is displayed by a LED, which has a current

rating less than 5mA, a resistor should be selected to

connect LED in series, for programming at the desired

current value. The resistor is calculated by the following

equation:

LED

−

When STAT pin is monitored by a processor, there should

be a 10k

Ω to 100kΩ pull-up resistor to connect the STAT

pin and the supply voltage of the processor.

Thermal Consideration

The most common measurement of package thermal

performance is thermal resistance measured from the

device junction to the air surrounding the package sur-

face (

JA). The θJA can be calculated by the following

equation:

−

where:

J= device junction temperature, maximum TJ=120°C

A= ambient temperature

D= device power dissipation

The device power dissipation, P

D, is a function of the

charge rate, the LDO output current and the voltages drop

across the internal FETs.

It can be calculated by the following equation:

LDO

LDOUT

LODIN

CHG

BATT

)

(

)

(

−

PCB Layout Consideration

Connecting the battery to BATT as close as possible pro-

vides accurate battery voltage sensing. The input and

output decoupling capacitors and the programmed re-

sistor R

SET should be placed as close as possible to the

device. The high current paths (VIN and LDOIN pins for

input and BATT and LDOOUT pins for output) must be

short and wide to minimize voltage drop.

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