AFE032 datasheet(34/77 Pages) TI1

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AFE032

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

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AFE032 Interrupts

The device contains three maskable interrupt signals: IFLAG_INT, TFLAG_INT, and DIG_ERR_INT. These

interrupt masks are set by default and can be changed by writing to the REG_FLAG_CTL register. The interrupt

masks are used to prevent any or all interrupt signals from commanding the active-low, open-drain interrupt pin

(INT). The REG_AFE_STATUS register contains the status of the three maskable interrupt signals; these signals

operate as follows:

•

IFLAG_INT: This interrupt is asserted when the PA goes to current limit mode for at least 16,384 DAC_CLK

cycles. If the PA goes to current limit mode but then falls out of current limit mode before 16,384 DAC_CLK

cycles have elapsed, then the IFLAG_INT is not set.

•

TFLAG_INT: This interrupt is asserted when the PA goes to overtemperature mode.

•

DIG_ERR_INT: This interrupt is a logical OR of all of individual interrupt vectors located in the

REG_DIG_ERR register. See the Digital Interrupt Bits section and Table 26 for more detalis.

Note that reading the REG_AFE_STATUS register resets the IFLAG_INT and TFLAG_INT bits. Similarly, reading

the REG_DIG_ERR register resets all of its bits. Note that the DIG_ERR_INT bit is not reset until the

REG_DIG_ERR register is read.

Digital Interrupt Bits

The device can identify certain errors that may be caused because of improper programming or clocking. These

errors are: AFIFO overflow, SPI write address fail, SPI illegal access, and SPI address error.

An AFIFO overflow error occurs if the ASYNCH FIFO used to convert DAC samples from the SPI to the DAC

clock domain has overflowed. This error indicates that the external DSP is transmitting DAC samples at a rate

(fS) higher than the maximum capability of the device DSP path for the current configuration. Refer to the SPI

Clock To DAC Clock Synchronization section for details on the proper selection of fS and XCLK.

An SPI write address fail error occurs when a read-only register is attempted to be written to. An SPI illegal

access error occurs when a reserved SPI register is attempted to be written to.

An SPI address error occurs when an SPI register is attempted to be accessed incorrectly. This error is caused

by several reasons: if a reserved SPI register is attempted to be written to, if an SPI register is attempted to be

accessed with an incorrect address (that is, an address that does not exist in Table 13), or if a read-only register

is attempted to be written to.

Initialization Sequence

The following initialization sequence must be performed (in addition to the sequence described in the Power-Up

Sequence section) to ensure the device is ready for communication to the power line each time power is applied

to the device and each time after a soft reset is performed:

•

Ensure the shutdown pin is low.

•

Ensure a valid XCLK signal is present.

•

Configure the device in SPI mode by taking the DAC pin low.

•

Wait for at least 65,536 XCLK cycles.

•

Enable the PA_NRF, TX_RX_NRF, and DAC_NRF blocks.

•

Configure the two programmable clock dividers.

•

Select the Tx filter band.

•

Set the Enable assist bit (bit 7 in the REG_HPF/LPF_CFG register).

•

Select which block in the digital path is used and which is bypassed.

•

If block 4 is included, program the block 4 parameter of the DSP path.

•

Set the Tx PGA, Rx PGA 1, and Rx PGA 2 gains.

•

Enable the low-pass filter (LPF) and high-pass filter (HPF) according to the application requirements by

writing to the REG_DAC/HPF/LPF/PA_CTL register. Make sure to enable the filter bias (bit 5 of the

REG_DAC/HPF/LPF/PA_CTL register).

•

Enable the DAC block by writing to register REG_DAC/HPF/LPF/PA_CTL (do not set the DAC pin high; just

enable the DAC block to ensure the block is ready when the device is configured for transmission).

•

Wait for two seconds to ensure all voltage references and signal path capacitors reach a steady state.

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