AFE032 datasheet(8/77 Pages) TI1

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AFE032

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

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ELECTRICAL CHARACTERISTICS: Digital

At TCASE = +25°C, VPAVS = 15 V, and VAVDD = VDVDD = 3.3 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (SCLK, DI, CS, SD, DAC, XCLK)

Leakage input current

0 V

≤ VIN ≤ DVDD

–1

0.01

µA

VIH

High-level input voltage

0.7 × DVDD

VIL

Low-level input voltage

0.3 × DVDD

SD pin high

SD > 0.7 × DVDD

Device in shutdown

SD pin function

(active high)

SD pin low

SD < 0.3 × DVDD

Device in normal operation

DAC pin high

DAC > 0.7 × DVDD

SPI access to DAC registers

DAC pin function

(active high)

DAC pin low

DAC < 0.3 × DVDD

SPI access to command and data registers

XCLK frequency range

XCLK jitter < 180 ps

MHz

DIGITAL OUTPUTS (DO, ZC_OUT)

VOH

High-level output voltage

IOH = 3 mA

DVDD – 0.4

DVDD

VOL

Low-level output voltage

IOL = –3 mA

GND

GND + 0.4

DIGITAL OUTPUTS (INT, TX_FLAG, RX_FLAG)

IOH

High-level output current

VOH = 3.3 V

µA

VOL

Low-level output voltage

IOL = 4 mA

0.4

IOL

Low-level output current

VOL = 400 mV

INT pin high

INT sink high < 1 µA

Normal operation

INT pin (active low,

open-drain)

INT pin low

INT < 0.4 V

Interrupt has occurred

TX_FLAG pin high

TX_FLAG sink high < 1 µA

Tx block disabled

TX_FLAG (active low,

open-drain)

TX_FLAG pin low

TX_FLAG < 0.4 V

Tx block ready

RX_FLAG pin high

RX_FLAG sink high < 1 µA

Rx block disabled

RX_FLAG (active

low, open-drain)

RX_FLAG pin low

RX_FLAG < 0.4 V

Rx block ready

GAIN TIMING

Gain select time

0.2

µs

SHUTDOWN MODE TIMING

Enable time

SD pin transitions from high to low

Disable time

SD pin transitions from low to high

POR TIMING

Power-on reset power-up time

DVDD

≥ 2 V

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