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3957 Datasheet(PDF) 9 Page - Allegro MicroSystems |
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3957 Datasheet(HTML) 9 Page - Allegro MicroSystems |
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9 / 16 page ![]() 3957 FULL-BRIDGE PWM MICROSTEPPING MOTOR DRIVER Functional Description Two A3957S— full-bridge PWM microstepping motor drivers are needed to drive the windings of a bipolar stepper motor. Internal pulse-width modulated (PWM) control circuitry regulates each motor winding’s current. The peak motor current is set by the value of an external current-sense resistor (RS), a reference voltage (VREF), and the digital-to-analog converter (DAC) data inputs (D0, D1, D2, and D3). To improve motor performance, especially when using sinusoidal current profiles necessary for microstepping, the A3957S— has three distinct current-decay modes: slow decay, fast decay, and mixed decay. PHASE Input. The PHASE input controls the direction of current flow in the load (table 1). An internally generated dead time of approximately 1.5 µs prevents crossover currents that could occur when switching the PHASE input. DAC Data Inputs (D0, D1, D2, D3). A non-linear DAC is used to digitally control the output current. The output of the DAC is used to set the trip point of the current-sense comparator. Table 3 shows DAC output voltages for each input condition. When D1, D2, and D3 are all logic low, all of the power output transistors are turned off. Internal PWM Current Control. Each motor driver IC contains an internal fixed off-time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink transistors are enabled and current flows through the motor winding and RS (figure 1). When the voltage across the sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source drivers (slow-decay mode) or the sink and source drivers (fast- or mixed-decay mode). With the DATA input lines tied to VCC, the maximum value of current limiting is set by the selection of RS and VREF with a transconductance function approximated by: ITRIP ≈ VREF/3RS = IOUT + ISO. where ISO is the sense-current offset due to the base-drive current of the sink transistor (typically 30 mA). The actual peak load current (IPEAK) will be slightly higher than ITRIP due to internal logic and switching delays. The driver(s) remain off for a time period determined by a user-selected external resistor-capacitor combination (RTCT). At the end of the fixed off time, the driver(s) are re-enabled, allowing the load current to increase to ITRIP again, maintaining an average load current. The current-sense comparator has a fixed offset of approxi- mately 16 mV. With RS = 0.5 Ω, the sense-current offset (ISO) is effectively cancelled (VIO(S) ≈ ISO • RS). The DAC data input lines are used to provide up to eight levels of output current. The internal 4-bit digital-to-analog converter reduces the reference input to the current-sense comparator in precise steps (the step reference current ratio or SRCR) to provide half-step, quarter-step, eighth-step, or “microstepping” load-current levels. ITRIP ≈ SRCR x VREF/3RS Slow Current-Decay Mode. When VPFD ≥ 3.5 V, the device is in slow current-decay mode (the source drivers are disabled when the load current reaches ITRIP). During the fixed off time, the load inductance causes the current to recirculate through the motor winding, sink driver, ground clamp diode, and sense resistor (see figure 1). Slow-decay mode produces low ripple current for a given fixed off time (see figure 2). Low ripple current is desirable because the average current in the motor winding is more nearly equal to the desired reference value, resulting in increased motor performance in microstepping applications. For a given level of ripple current, slow decay affords the lowest PWM frequency, which reduces heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. Slow decay also has the advantage that the PWM load current regulation can follow a more rapidly increasing reference before the PWM frequency drops into the audible range. For these reasons slow-decay mode is typically used as long as good current regulation can be maintained. Figure 1 — Load-Current Paths Dwg. EP-006-15 R S BB V DRIVE CURRENT RECIRCULATION (SLOW-DECAY MODE) RECIRCULATION (FAST-DECAY MODE) |
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