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LMP91050 Datasheet(PDF) 7 Page - Texas Instruments |
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LMP91050 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 23 page ![]() Valid Data tH tSU tPH tPL SDI 16 th clock SCLK Valid Data LMP91050 www.ti.com SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013 Timing Characteristics (1) (continued) The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless otherwise specified. All other limits apply to TA = TJ = +25°C. Min Typ Max Symbol Parameter Conditions Units (2) (3) (2) tPH SCLK Pulse Width High 0.4/fSCLK ns tPL SCLK Pulse Width Low 0.4/fSCLK ns tCSS CSB Setup Time 10 ns tCSH CSB Hold Time 10 ns SDI Setup Time prior to rise tSU 10 ns edge of SCLK SDI Hold Time prior to rise tSH 10 ns edge of SCLK SDO Disable Time after rise tDOD1 45 ns edge of CSB SDO Disable Time after 16th tDOD2 45 ns rise edge of SCLK SDO Enable Time from the fall tDOE 35 ns edge of 8th SCLK SDO Access Time after the fall tDOA 35 ns edge of SCLK SDO hold time after the fall tDOH 5 ns edge of SCLK tDOR SDO Rise time 5 ns tDOF SDO Fall time 5 ns Timing Diagrams Figure 3. SPI Timing Diagram Figure 4. SPI Set-up Hold Time Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMP91050 |
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