AM79C960KC datasheet(32/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-374

Am79C960

DETAILED FUNCTIONS

Bus Interface Unit (BIU)

The bus interface unit is a mixture of a 20 MHz state ma-

chine and asynchronous logic. It handles two types of

accesses: accesses where the PCnet-ISA controller is

a slave and accesses where the PCnet-ISA controller is

the Current Master.

In slave mode, signals like

IOCS16 are asserted and

deasserted as soon as the appropriate inputs are re-

ceived. IOCHRDY is asynchronously driven LOW if the

PCnet-ISA controller needs a wait state. It is released

synchronously when the PCnet-ISA controller is ready.

When the PCnet-ISA controller is the Current Master, all

the signals it generates are synchronous to the on-chip

20 MHz clock.

DMA Transfers

The BIU will initiate DMA transfers according to the type

of operation being performed. There are three primary

types of DMA transfers:

1. Initialization Block DMA Transfers

Once the BIU has been granted bus mastership, it will

perform four data transfer cycles (eight bytes) before re-

linquishing the bus. The four transfers within the

mastership period will always be read cycles to contigu-

ous addresses. There are 12 words to transfer so there

will be three bus mastership periods.

2. Descriptor DMA Transfers

Once the BIU has been granted bus mastership, it will

perform the appropriate number of data transfer cycles

before relinquishing the bus. The transfers within the

mastership period will always be of the same type

(either all read or all write), but may be to non-

contiguous addresses. Only the bytes which need to be

read or written are accessed.

3. Burst-Cycle DMA Transfers

Once the BIU has been granted bus mastership, it will

perform a series of consecutive data transfer cycles be-

fore relinquishing the bus. Each data transfer will be

performed sequentially, with the issue of the address,

and the transfer of the data with appropriate output sig-

nals to indicate selection of the active data bytes during

the transfer. All transfers within the mastership cycle will

be either read or write cycles, and will be to contiguous

addresses. The number of data transfer cycles within

the burst is dependent on the programming of the

DMAPLUS option (CSR4, bit 14).

If DMAPLUS = 0, a maximum of 16 transfers will be per-

formed. This may be changed by writing to the burst

amount of time as the Am2100 family of LANCE-based

boards, a little over 5 microseconds.

If DMAPLUS = 1, the burst will continue until the FIFO is

filled to its high threshold (32 bytes in transmit opera-

tion) or emptied to its low threshold (16 bytes in receive

operation). The exact number of transfer cycles in this

case will be dependent on the latency of the system bus

to the BIU’s mastership request and the speed of bus

operation.

Buffer Management Unit (BMU)

The buffer management unit is a micro-coded 20 MHz

state machine which implements the initialization block

and the descriptor architecture.

Initialization

PCnet-ISA controller initialization includes the reading

of the initialization block in memory to obtain the operat-

ing parameters. The initialization block is read when the

INIT bit in CSR0 is set. The INIT bit should be set before

or concurrent with the STRT bit to insure correct opera-

tion. Four words at a time are read and the bus is

released at the end of each block of reads, for a total of

three arbitration cycles. Once the initialization block has

been read in and processed, the BMU knows where the

receive and transmit descriptor rings are. On completion

of the read operation and after internal registers have

been updated, IDON will be set in CSR0, and an inter-

rupt generated if IENA is set.

The Initialization Block is vectored by the contents of

CSR1 (least significant 16 bits of address) and CSR2

(most significant 8 bits of address). The block contains

the user defined conditions for PCnet-ISA controller op-

eration,

together

with

the

address

and

length

information to allow linkage of the transmit and receive

descriptor rings.

There is an alternative method to initialize the

PCnet-ISA controller. Instead of initialization via the

initialization block in memory, data can be written di-

rectly into the appropriate registers. Either method may

be used at the discretion of the programmer. If the regis-

ters are written to directly, the INIT bit must not be set, or

the initialization block will be read in, thus overwriting

the previously written information. Please refer to

Appendix C for details on this alternative method.

Reinitialization

The transmitter and receiver section of the PCnet-ISA

controller can be turned on via the initialization block

(MODE Register DTX, DRX bits CSR15[1:0]). The state

of the transmitter and receiver are monitored through

CSR0 (RXON, TXON bits). The PCnet-ISA controller

should be reinitialized if the transmitter and/or the re-

ceiver were not turned on during the original initialization

and it was subsequently required to activate them, or if

either section shut off due to the detection of an error

condition (MERR, UFLO, TX BUFF error).

Reinitialization may be done via the initialization block or

by setting the STOP bit in CSR0, followed by writing to

CSR15, and then setting the START bit in CSR0. Note

that this form of restart will not perform the same in the

PCnet-ISA controller as in the LANCE. In particular, the

PCnet-ISA controller reloads the transmit and receive

descriptor pointers with their respective base ad-

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