AM79C960KC datasheet(79/127 Pages) AMD

79 / 127 page

P R E L I M I N A R Y

AMD

1-421

Am79C960

buffer, it must not change any

field in the descriptor entry.

ERR

ERR is the OR of FRAM, OFLO,

CRC, or BUFF. ERR is written by

the PCnet-ISA controller.

FRAM

FRAMING

ERROR

indicates

that the incoming frame con-

tained a non-integer multiple of

eight bits and there was an FCS

error. If there was no FCS error

on the incoming frame, then

FRAM will not be set even if there

was a non integer multiple of

eight bits in the frame. FRAM is

not valid in internal loopback

mode. FRAM is valid only when

ENP is set and OFLO is not.

FRAM is written by the PCnet-

ISA controller.

OFLO

OVERFLOW error indicates that

the receiver has lost all or part of

the incoming frame, due to an in-

ability to store the frame in a

memory buffer before the inter-

nal FIFO overflowed. OFLO is

valid only when ENP is not set.

OFLO is written by the PCnet-

ISA controller.

CRC

CRC indicates that the receiver

has detected a CRC (FCS) error

on the incoming frame. CRC is

valid only when ENP is set and

OFLO is not. CRC is written by

the PCnet-ISA controller.

BUFF

BUFFER ERROR is set any time

the PCnet-ISA controller does

not own the next buffer while data

chaining a received frame. This

can occur in either of two ways:

1) The OWN bit of the next

buffer is zero.

2) FIFO overflow occurred

before the PCnet-ISA

controller polled the next

descriptor.

If a Buffer Error occurs, an Over-

flow

Error

may

also

occur

internally in the FIFO, but will not

be reported in the descriptor

status entry unless both BUFF

and OFLO errors occur at the

same time. BUFF is written by

the PCnet-ISA controller.

STP

START OF PACKET indicates

that this is the first buffer used by

the PCnet-ISA controller for this

frame. It is used for data chaining

buffers. STP is written by the

PCnet-ISA controller.

ENP

END OF PACKET indicates that

this is the last buffer used by the

PCnet-ISA controller for this

frame. It is used for data chaining

buffers. If both STP and ENP are

set, the frame fits into one buffer

and there is no data chaining.

ENP is written by the PCnet-ISA

controller.

7-0

HADR

The HIGH ORDER 8 address

bits of the buffer pointed to by this

descriptor. This field is written by

the host and is not changed by

the PCnet-ISA controller.

RMD2

Bit

Name

Description

15-12 ONES

MUST BE ONES. This field is

written by the host and un-

changed

the

PCnet-ISA

controller.

11-0

BCNT

BUFFER BYTE COUNT is the

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length

of the buffer. This field is written

by the host and is not changed by

the PCnet-ISA controller.

RMD3

Bit

Name

Description

15-12

RES

RESERVED and read as zeros.

11-0

MCNT

MESSAGE BYTE COUNT is the

length in bytes of the received

message, expressed as an un-

signed binary integer. MCNT is

valid only when ERR is clear and

ENP is set. MCNT is written by

the PCnet-ISA controller and

cleared by the host.

Transmit Descriptors

The Transmit Descriptor Ring Entries (TDREs) are com-

posed of 4 transmit message fields (TMD0-3). Together

they contain the following information:

s The address of the actual message data buffer in

user or host memory.

s The length of the message buffer.

s Status information indicating the condition of the

buffer. The eight most significant bits of TMD1

(TMD1[15:8]) are collectively termed the STATUS

of the transmit descriptor.

AM79C960KC Datasheet(PDF) 79 Page - Advanced Micro Devices

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