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AM79C960KC Datasheet(PDF) 92 Page - Advanced Micro Devices

Part # AM79C960KC
Description  PCnetTM-ISA Single-Chip Ethernet Controller
PDF  127 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C960KC Datasheet(HTML) 92 Page - Advanced Micro Devices

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P R E L I M I N A R Y
AMD
1-434
Am79C960
SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Master Mode Bus Release
tMMBR1
Command Deassert to
↓ DRQ
45
65
ns
tMMBR2
↓ DRQ to ↑ DACK
0ns
tMMBR3
↓ DRQ to ↑ MASTER
40
60
ns
tMMBR4
↓ DRQ to Command, SBHE,
SA0–19, LA17–23 Tristated,
–15
0
ns
Master Write Cycles
tMMW1
SBHE, SA0–19, LA17–23,
Active to
↓ MEMW
(Note 1)
EXTIME + 45
EXTIME + 65
ns
tMMW2
MEMW Active
(Note 2)
MSWRA – 10
MSWRA + 5
ns
tMMW3
MEMW Inactive
(Note 1)
EXTIME + 97
EXTIME + 105
ns
tMMW4
↑ MEMW to SBHE, SA0–19,
LA17–23,SD Inactive
45
55
ns
tMMW5
SBHE, SA0–19, LA17–23, SD
Hold After
↑ MEMW
45
60
ns
tMMW6
SBHE, SA0–19, LA17–23,
SD Setup to
↓ MEMW
(Note 1)
EXTIME + 45
EXTIME + 55
ns
tMMW7
↓ IOCHRDY Delay
From
↓ MEMW
tMMW2 – 175
ns
tMMW8
IOCHRDY Inactive
55
ns
tMMW9
↑ IOCHRDY to ↑ MEMW
130
ns
tMMW10
SD Active to
↓ MEMW
(Note 1)
EXTIME + 20
EXTIME + 60
ns
tMMW11
SD Setup to
↓ MEMW
(Note 1)
EXTIME + 20
EXTIME + 60
ns
Master Read Cycles
tMMR1
SBHE, SA0–19, LA17–23,
Active to
↓ MEMR
(Note 1)
EXTIME + 45
EXTIME + 60
ns
tMMR2
MEMR Active
(Note 2)
MSRDA – 10
MSRDA + 5
ns
tMMR3
MEMR Inactive
(Note 1)
EXTIME + 97
EXTIME + 105
ns
tMMR4
↑ MEMR to SBHE, SA0–19,
LA17–23 Inactive
45
55
ns
tMMR5
SBHE, SA0–19, LA17–23
Hold After
↑ MEMW
45
55
ns
tMMR6
SBHE, SA0–19, LA17–23
Setup to
↓ MEMR
(Note 1)
EXTIME + 45
EXTIME + 55
ns
tMMR7
↓ IOCHRDY Delay From
↓ MEMR
tMMR2 – 175
ns
tMMR8
IOCHRDY Inactive
55
ns
tMMR9
↑ IOCHRDY to ↑ MEMR
130
ns
tMMR10
SD Setup to
↑ MEMR
30
ns
tMMR11
SD Hold After
↑ MEMR
0ns



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