AM79C960KC datasheet(51/127 Pages) AMD

51 / 127 page

P R E L I M I N A R Y

AMD

1-393

Am79C960

Current Master Operation

Current Master operation only occurs in the bus master

mode. It does not occur in shared memory mode.

There are three phases to the use of the bus by the

PCnet-ISA controller as Current Master, the Obtain

Phase, the Access Phase, and the Release Phase.

Obtain Phase

A Master Mode Transfer Cycle begins by asserting

DRQ. When the Permanent Master asserts

DACK, the

PCnet-ISA controller asserts

MASTER, signifying it has

taken control of the ISA bus. The Permanent Master tris-

tates the address, command, and data lines within 60 ns

DACK going active. The Permanent Master drives

AEN inactive within 71 ns of

MASTER going active.

Access Phase

The ISA bus requires a wait of at least 125 ns after

MASTER is asserted before the new master is allowed

to drive the address, command, and data lines. The

PCnet-ISA controller will actually wait 3 clock cycles or

150 ns.

The following signals are not driven by the Permanent

Master and are simply pulled HIGH: BALE, IOCHRDY,

IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISA

controller assumes the memory which it is accessing is

16 bits wide and can complete an access in the time pro-

grammed for the PCnet-ISA controller

MEMR and

MEMW signals. Refer to the ISA Bus Configuration

Release Phase

When the PCnet-ISA controller is finished with the bus,

it drives the command lines inactive. 50 ns later, the con-

troller tri-states the command, address, and data lines

and drives DRQ inactive. 50 ns later, the controller

drives

MASTER inactive.

At least 375 ns after DRQ goes inactive, the Permanent

Master drives

DACK inactive.

The Permanent Master drives AEN active within 71 ns of

MASTER going inactive. The Permanent Master is al-

lowed to drive the command lines no sooner than 60 ns

after

DACK goes inactive.

Master Mode Memory Read Cycle

After the PCnet-ISA controller has acquired the ISA bus,

it can perform a memory read cycle. All timing is gener-

ated relative to the 20 MHz clock (network clock). Since

there is no way to tell if memory is 8- or 16-bit or when it

is ready, the PCnet-ISA controller by default assumes

16-bit, 1 wait state memory. The wait state assumption

is based on the default value in the MSRDA register in

ISACSR0.

The cycle begins with SA0-19,

SBHE, and LA17-23 be-

ing presented. The ISA bus requires them to be valid for

at least 28 ns before a read command and the

PCnet-ISA controller provides one clock or 50 ns of

setup time before asserting

MEMR.

The ISA bus requires

MEMR to be active for at least

219 ns, and the PCnet-ISA controller provides a default

of 5 clocks, or 250 ns, but this can be tuned for faster

systems with the Master Mode Read Active (MSRDA)

LOW, the PCnet-ISA controller will wait. The wait state

counter must expire and IOCHRDY must be HIGH for

the PCnet-ISA controller to continue.

The PCnet-ISA controller then accepts the memory

read data. The ISA bus requires all command lines to re-

main inactive for at least 97 ns before starting another

bus cycle and the PCnet-ISA controller provides at least

two clocks or 100 ns of inactive time.

The ISA bus requires read data to be valid no more than

173 ns after receiving

MEMR active and the PCnet-ISA

controller requires 10 ns of data setup time. The ISA bus

requires read data to provide at least 0 ns of hold time

and to be removed from the bus within 30 ns after

MEMR goes inactive. The PCnet-ISA controller requires

0 ns of data hold time.

Master Mode Memory Write Cycle

After the PCnet-ISA controller has acquired the ISA bus,

it can perform a memory write cycle. All timing is gener-

ated relative to a 20 MHz clock which happens to be the

same as the network clock. Since there is no way to tell if

memory is 8- or 16-bit or when it is ready, the PCnet-ISA

controller by default assumes 16-bit, 1 wait state mem-

ory. The wait state assumption is based on the default

value in the MSWRA register in ISACSR1.

The cycle begins with SA0-19,

SBHE, and LA17-23 be-

ing presented. The ISA bus requires them to be valid at

least 28 ns before

MEMW goes active and data to be

valid at least 22 ns before

MEMW goes active. The

PCnet-ISA controller provides one clock or 50 ns of

setup time for all these signals.

The ISA bus requires

MEMW to be active for at least

219 ns, and the PCnet-ISA controller provides a default

of 5 clocks, or 250 ns, but this can be tuned for faster

systems with the Master Mode Write Active (MSWRA)

the PCnet-ISA controller will wait. IOCHRDY must be

HIGH for the PCnet-ISA controller to continue.

The ISA bus requires data to be valid for at least 25 ns

after

MEMW goes inactive, and the PCnet-ISA control-

ler provides one clock or 50 ns.

The ISA bus requires all command lines to remain inac-

tive for at least 97 ns before starting another bus cycle.

The PCnet-ISA controller provides at least two clocks or

100 ns of inactive time when bit 4 in ISACSR2 is set. The

EISA bus requires all command lines to remain inactive

for at least 170 ns before starting another bus cycle.

When bit 4 in ISACSR4 is cleared, the PCnet-ISA con-

troller provides 200 ns of inactive time.

AM79C960KC Datasheet(PDF) 51 Page - Advanced Micro Devices

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