AM79C960KC datasheet(85/127 Pages) AMD

85 / 127 page

P R E L I M I N A R Y

AMD

1-427

Am79C960

SYSTEM APPLICATION

ISA Bus Interface

Compatibility Considerations

Although 8 MHz is now widely accepted as the standard

speed at which to run the ISA bus, many machines have

been built which operate at higher speeds with non-

standard timing. Some machines do not correctly

support 16-bit I/O operations with wait states. Although

the PCnet-ISA controller is quite fast, some operations

still require an occasional wait state. The PCnet-ISA

controller moves data through memory accesses, there-

fore, I/O operations do not affect performance. By

configuring the PCnet-ISA controller as an 8-bit I/O de-

vice, compatibility with PC/AT-class machines is

obtained at virtually no cost in performance. To treat the

PCnet-ISA controller as an 8-bit software resource (for

non-ISA applications), the even-byte must be accessed

first, followed by an odd-byte access.

Memory cycle timing is an area where some tradeoffs

may be necessary. Any slow down in a memory cycle

translates directly into lower bandwidth. The PCnet-ISA

controller starts out with much higher bandwidth than

most slave type controllers and should continue to be

superior even if an extra 50 or 100 ns are added to mem-

ory cycles.

The memory cycle active time is tunable in 50 ns incre-

ments with a default of 250 ns. The memory cycle idle

time defaults to 200 ns and can be reprogrammed to

100 ns. See register description for ISACS42. Most ma-

chines should not need tuning.

The PCnet-ISA controller is compatible with NE2100

and NE1500T software drivers. All the resources such

as address PROM, boot PROM, RAP, and RDP are in

the same location with the same semantics. An addi-

tional set of registers (ISA CSR) is available to configure

on board resources such as ISA bus timing and LED op-

eration. However, loopback frames for the PCnet-ISA

controller must contain more than 64 bytes of data if the

Runt Packet Accept feature is not enabled; this size limi-

tation does not apply to LANCE (Am7990) based boards

such as the NE2100 and NE1500T.

Bus Master

Bus Master mode is the preferred mode for client appli-

cations on PC/AT or similar machines supporting 16-bit

DMA with its unsurpassed combination of high perform-

ance and low cost.

Shared Memory

The shared memory mode is recommended for file serv-

ers or other applications where there is very high,

average or peak latency.

The address compare circuit has the following

functions. It receives the 7 LA signals, generates

MEMCS16, and compares them to the desired shared

memory and boot PROM addresses. The logic latches

the address compare result when BALE goes inactive

and uses this result along with

REF (must be deas-

serted) and the appropriate SA signals to generate

SMAM and BPAM.

All these functions can be performed in one PAL device.

Assume both memories are 8 Kbytes and are in the

same 128 Kbyte region. SA16,15,14,13 are required to

select 8 Kbytes, and there are 7 LA pins. Counting the

MEMCS16 pin, the latched compare pin, four SA pins,

the

REF pin, the SMAM pin and the BPAM pin, we find a

total of 16 pins which can easily fit into one PAL device.

To operate in an 8–bit PC/XT environment, the LA

signals should have weak pull-down resistors con-

nected to them to present a logic 0 level when not driven.

SD0–15

SA0–19

LA17–23

PRDB0–7

APCS

BPCS

D0–7

A0–X

D0–7

ISA

Bus

16-Bit System Data

24-Bit System

Address

PCnet-ISA

Controller

8-Bit Private Data

Ethernet

Address

PROM

Boot

PROM

16907B-5

Bus Master Block Diagram

AM79C960KC Datasheet(PDF) 85 Page - Advanced Micro Devices

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