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AM79C974 Datasheet(PDF) 34 Page - Advanced Micro Devices |
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AM79C974 Datasheet(HTML) 34 Page - Advanced Micro Devices |
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34 / 153 page ![]() AMD P R E L I M I N A R Y 34 Am79C974 Basic Non-Burst Write All Am79C974 controller non-burst write accesses are of the PCI command type Memory Write (type 7). Figure 8 shows two non-burst write access within one arbitration cycle. The Am79C974 controller will drop FRAME between two consecutive non-burst write cy- cles. The Am79C974 controller will re-request the bus immediately if it is preempted before starting the second access. The example below shows an extended cycle for the first access. The target asserts DEVSEL 2 clock cycles after the address phase ( FRAME asserted) and adds one extra wait state by asserting TRDY only on clock 7. The second write cycle in the example shows a ZERO wait state access. 18681A-12 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 12345678 ADDR BE's 0111 9 PAR PAR PAR DATA ADDR DATA BE's 0111 PAR PAR 10 11 DEVSEL is sampled by the Am79C974 controller. Figure 8. Non-Burst Write Cycles With and Without Wait States |
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