AM79C974 datasheet(54/153 Pages) AMD

54 / 153 page

AMD

P R E L I M I N A R Y

Am79C974

the controller portion of the Am79C974 controller sees

the first ISRDCLK transition. This also strobes in the in-

coming fifth bit to the MENDEC as Manchester “1”.

IRXDAT may make a transition after the ISRDCLK rising

edge in bit cell 5, but its state is still undefined. The

Manchester “1” at bit 5 is clocked to IRXDAT output at

1/4 bit time in bit cell 6.

PLL Tracking

After clock acquisition, the phase-locked clock is com-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a cor-

rection circuit. This circuit ensures that the phase-

locked clock remains locked on the received signal.

Individual bit cell phase corrections of the Voltage Con-

trolled Oscillator (VCO) are limited to 10% of the phase

difference between BCC and phase-locked clock.

Hence, input data jitter is reduced in ISRDCLK by

10 to 1.

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI

± inputs after

IRXCRS is asserted for an end of message. IRXCRS

de-asserts 1 to 2 bit times after the last positive transi-

tion on the incoming message. This initiates the end of

reception cycle. The time delay from the last rising edge

of the message to IRXCRS de-assert allows the last bit

to be strobed by ISRDCLK and transferred to the con-

troller section, but prevents any extra bit(s) at the end

of message.

Data Decoding

The data receiver is a comparator with clocked output to

minimize noise sensitivity to the DI

± inputs. Input error is

less than

±35 mV to minimize sensitivity to input rise and

fall time. ISRDCLK strobes the data receiver output at

1/4 bit time to determine the value of the Manchester bit,

and clocks the data out on IRXDAT on the following

ISRDCLK. The data receiver also generates the signal

used for phase detector comparison to the internal

MENDEC voltage controlled oscillator (VCO).

Differential Input Terminations

The differential input for the Manchester data (DI

±)

should be externally terminated by two 40.2

Ω ±1% re-

sistors and one optional common-mode bypass capaci-

tor, as shown in the Differential Input Termination

diagram below. The differential input impedance, ZIDF,

and the common-mode input impedance, ZICM, are

specified so that the Ethernet specification for cable ter-

mination impedance is met using standard 1% resistor

terminators. If SIP devices are used, 39

Ω is the nearest

usable value. The CI

± differential inputs are terminated

in exactly the same way as the DI

± pair.

18681A-24

Am79C974

DI+

DI-

40.2

Ω

40.2

Ω

0.01

µF

0.1

µF

AUI Isolation

Transformer

Figure 20. Differential Input Termination

AM79C974 Datasheet(PDF) 54 Page - Advanced Micro Devices

AM79C974 Datasheet(HTML) 54 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL