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AM79C974 Datasheet(PDF) 38 Page - Advanced Micro Devices |
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AM79C974 Datasheet(HTML) 38 Page - Advanced Micro Devices |
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38 / 153 page  AMD P R E L I M I N A R Y 38 Am79C974 Disconnect Without Data Transfer Figure 12 shows a target disconnect sequence during which no data is transferred. STOP is asserted on clock 4 without TRDY being asserted at the same time. The Am79C974 controller terminates the current transfer with the deassertion of FRAME on clock 5 and one clock cycle later with the deassertion of IRDY. It finally re- leases the bus on clock 6. The Am79C974 controller will re-request the bus after 2 clock cycles to retry the last transfer. The starting address of the new transfer will be the same address as of the last untransferred data. 18681A-16 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 1234567 8 DATA 0000 0111 10 9 PAR PAR PAR DEVSEL is sampled by the Am79C974 controller. STOP 0111 11 ADDRi ADDRi Figure 12. Disconnect Without Data Transfer |
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