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AM79C975VCW Datasheet(PDF) 206 Page - Advanced Micro Devices |
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AM79C975VCW Datasheet(HTML) 206 Page - Advanced Micro Devices |
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206 / 304 page ![]() 206 Am79C973/Am79C975 P R E L I M INARY RMD0 Bit Name Description 31-0 RBADR Receive Buffer address. This field contains the address of the re- ceive buffer that is associated with this descriptor. RMD1 Bit Name Description 31 OWN This bit indicates whether the de- scriptor entry is owned by the host (OWN = 0) or by the Am79C973/Am79C975 controller (OWN = 1). The Am79C973/ Am79C975 controller clears the OWN bit after filling the buffer that the descriptor points to. The host sets the OWN bit after emptying the buffer. Once the Am79C973/Am79C975 controller or host has relin- quished ownership of a buffer, it must not change any field in the descriptor entry. 30 ERR ERR is the OR of FRAM, OFLO, CRC, BUFF, or BPE. ERR is set by the Am79C973/Am79C975 controller and cleared by the host. 29 FRAM Framing error indicates that the incoming frame contains a non- integer multiple of eight bits and there was an FCS error. If there was no FCS error on the incom- ing frame, then FRAM will not be set even if there was a non- integer multiple of eight bits in the frame. FRAM is not valid in inter- nal loopback mode. FRAM is val- id only when ENP is set and OFLO is not. FRAM is set by the Am79C973/Am79C975 controller and cleared by the host. 28 OFLO Overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inabili- ty to move data from the receive FIFO into a memory buffer before the internal FIFO overflowed. OFLO is set by the Am79C973/ Am79C975 controller and cleared by the host. 27 CRC CRC indicates that the receiver has detected a CRC (FCS) error on the incoming frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the Am79C973/Am79C975 controller and cleared by the host. CRC will also be set when Am79C973/ Am79C975 receives an RX_ER indication from the external PHY through the MII. 26 BUFF Buffer error is set any time the Am79C973/Am79C975 controller does not own the next buffer Table 59. Receive Descriptor (SWSTYLE = 2) Address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0 CRDA+00h RBADR[31:0] CRDA+04h OWN ERR FRA M OFL O CRC BUF F STP ENP BPE PAM LAFM BAM RES 1111 BCNT CRDA+08h RES RFRTAG[14:0] 0000 MCNT CRDA+0Ch USER SPACE Table 60. Receive Descriptor (SWSTYLE = 3) Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-0 CRDA+00h RES RES RES 0000 MCNT CRDA+04h OWN ERR FRAM OFLO CRC BUFF STP ENP BPE RES 1111 BCNT CRDA+08h RBADR[31:0] CRDA+0Ch USER SPACE |
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