AM79C975VCW datasheet(202/304 Pages) AMD

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202

Am79C973/Am79C975

P R E L I M INARY

ANR18: Descrambler Resynchronization Timer

Descrambler Resynchronization Timer Register

(shown in Table 51) allows the user to program the time

it takes for the descrambler to start the resynchroniza-

tion process. This is to ensure that the Descrambler re-

synchronizes itself to the next IDLE symbol stream

after it receives a packet of excessive length. This reg-

ister should be programmed as described in the Table

51. The programmed timer value should always be

greater than the length of the maximum size packet in

normal operation.

Table 51. ANR18: Descrambler Resynchronization Timer (Register 18)

Note:

1. The corresponding time to this setting is 1ms.

ANR19: PHY Management Extension Register

(Register 19)

Table 52 contains the PHY Management Extension

Table 52. ANR19: PHY Management Extension Register (Register 19)

ANR24: Summary Status Register (Register 24)

The Summary Status register is a global register con-

taining status information. This register is Read/Only

and represents the most important data which a single

ister indicates the following: Link Status, Full Duplex

Status, Auto-Negotiation Alert, and Speed. See Table

53.

Reg

Bits

Name

Description

Read/

Write

Default

Value

Soft

Reset

15-0

Descrambler Resynch Timer

Each bit indicates 4 clocks, or 160

ns. The count decrements from a

default value of 1 ms or an initial

value loaded by the user. This

counter provides a maximum timer

value of 10.5 ms.

R/W

000110000

1101010

(Note 1)

0001100

0011010

(Note 1)

Reg

Bits

Name

Description

Read/Write

Default Value

Soft Reset

15:6

Reserved

Write as 0, ignore on read.

Mgmt Frame

Format

1 = last management frame

was invalid (opcode error, etc.);

0 = last management frame

was valid.

4-0

PHY Address

PHY Address defaults to

11110.

11110

Retains

Value

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