AM79C975VCW datasheet(200/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

ANR16: INTERRUPT Status and Enable Register (Register 16)

The Interrupt bits indicate when there is a change in the

Link Status, Duplex Mode, Auto-Negotiation status, or

Speed status. Register 16 contains the interrupt status

and interrupt enable bits. The status is always updated

whether or not the interrupt enable bits are set. When

an interrupt occurs, the system will need to read the in-

terrupt register to clear the status bits and determine

the course of action needed. See Table 49.

Table 49. ANR16: INTERRUPT Status and Enable Register (Register 16)

Note:

1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.

ANR17: PHY Control/Status Register (Register 17)

This register is used to control the configuration of the

10/100 PHY unit of the Am79C973/Am79C975 device.

See Table 50.

When configuring the device to enable/disable the

scrambler/descrambler (SDISSCR), and/or to enable/

disable the alignment (SDISALIGN), a software reset

after a write operation to the appropriate bits in this reg-

ister is mandatory for proper configuration. If a register

bit is only appropriate to use at one speed, then the

speed will be indicated in parenthesis in the Name col-

umn, for example, (10M).

Bit(s)

Name

Description

Read/

Write

H/W or Soft

Reset

15:14

Reserved

Interrupt Test Enable

(Note 1)

1 = When this bit is set, setting bits 12:9 of this register

will cause an INTR condition and will set bits 4:1

accordingly. The effect is to test the register bits with

a forced interrupt condition.

0 = Bits 4:1 are only set if the interrupt condition (if any

bits in 12:9 are set) occurs.

R/W

Link Status Change

Interrupt Enable

1 = Link Status Change

0 = This interrupt is masked.

R/W

Duplex Mode Change

Interrupt Enable

1 = Duplex Mode Change

0 = This interrupt is masked.

R/W

Auto-Neg Change

Interrupt Enable

1 = Auto-Neg Change

0 = This interrupt is masked.

R/W

Speed Change

Interrupt Enable

1 = Speed Change

0 = This interrupt is masked.

R/W

Global

Interrupt Enable

1= Global Interrupt

0 = This interrupt is masked.

R/W

7:5

Reserved

Link Status Change

Interrupt

1 = Link Status has changed on a port.

0 = No change in Link Status

RO,

Duplex Mode Change

Interrupt

1 = Duplex Mode has changed on a port

0 = No change in Duplex mode

RO,

Auto-Neg Change

Interrupt

1 = Auto-Neg status has changed on a port

0 = No change in Auto-Neg status

RO,

Speed Change

Interrupt

1 = Speed status has changed on a port

0 = No change

RO,

Global

Interrupt

1 = Indicates a change in status of any of the above

interrupts

0 = Indicates no change in Interrupt Status

RO,

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