AM79C975VCW datasheet(201/304 Pages) AMD

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Am79C973/Am79C975

201

P R E L I M INARY

Table 50. ANR17: PHY Control/Status Register (Register 17)

Reg

Bits

Name

Description

Read/Write

H/W

Reset

Soft Reset

SDISALIGN

(100M)

1 = pass unaligned data to internal PHY

0 = enable alignment block

R/W

Retains

Value

SDISSCR

(100M)

1 = disable scrambler/descrambler

0 = enable scrambler/descrambler

R/W

Retains

Value

Force Link Good

Enable

1 = link status forced to link up state.

0 = link status is determined by the device.

R/W

Disable Link Pulse

(10M)

1 = Link pulses sent from the

10BASE-T transmitter are suppressed.

R/W

SQE_TEST Disable

(10M)

1 = Disables the SQE heartbeat which

occurs after each 10BASE-T transmission.

0 = The heart beat assertion occurs on the

COL pin approximately 1 µs after

transmission and for a duration of 1 µs.

R/W

EN_FEFI

(100M)

1 = enable FEFI, 0 = disable FEFI

This bit is ignored if auto-neg is enabled.

R/W

Jabber Detect

Disable (10M)

1 = disable jabber detect

0 = enable jabber detect

R/W

8:7

LBK[1-0]

(100M)

00 = normal operation

01 = unused

10 = unused

11 = serial loopback

R/W

Receive Polarity

Reversed

(10M)

1 = Receive polarity of the 10BASE-T

receiver is reversed.

0 = Receive polarity is correct.

Auto Receive

Polarity Correction

Disable (10M)

1 = polarity correction circuit is disabled for

10BASE-T.

0 = Self correcting polarity circuit is enabled

R/W

Extended Distance

Enable

(10M)

1 = 10BASE-T receive squelch thresholds

are reduced to allow reception of frames

which are greater than 100 meters.

0 = Squelch thresholds are set for standard

distance of 100 meters.

R/W

TX_DISABLE

1 = TX± outputs not active for MLT-3 and

10BASE-T. TX± outputs to logical “0” for

PECL.

0 = Transmit valid data.

R/W

TX_CRS

1 = CRS is asserted when transmit or

receive medium is active.

0 = CRS is asserted when receive medium

is active.

Reserved

Reserved.

PHY Isolated

1 = Internal PHY is isolated

0 = Internal PHY is enabled

0/1

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