AM79C975VCW datasheet(211/304 Pages) AMD

211 / 304 page

Am79C973/Am79C975

211

P R E L I M INARY

when a parity error occurred on

the bus interface during a data

transfers from the transmit buffer

associated with this descriptor.

The Am79C973/Am79C975 con-

troller will only set BPE when the

advanced parity error handling is

enabled by setting APERREN

(BCR20, bit 10) to 1. BPE is set

the

Am79C973/Am79C975

controller and cleared by the

host.

This bit does not exist, when the

Am79C973/Am79C975 controller

is programmed to use 16-bit soft-

ware structures for the descriptor

ring entries (BCR20, bits 7-0,

SWSTYLE is cleared to 0).

22-16 RES

Reserved locations.

15-12 ONES

These four bits must be written as

ones. This field is written by the

host

and

unchanged

the

Am79C973/Am79C975

control-

ler.

11-00 BCNT

Buffer Byte Count is the usable

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length of

the buffer. This is the number of

bytes from this buffer that will be

transmitted by the Am79C973/

Am79C975 controller. This field is

written by the host and is not

changed

the

Am79C973/

Am79C975 controller. There are

no minimum buffer size restric-

tions.

TMD2

Bit

Name

Description

BUFF

Buffer

error

set

the

Am79C973/Am79C975 controller

during transmission when the

Am79C973/Am79C975 controller

does not find the ENP flag in the

current descriptor and does not

own the next descriptor. This can

occur in either of two ways:

1. The OWN bit of the next buffer

is 0.

2. FIFO underflow occurred be-

fore the Am79C973/Am79C975

controller obtained the STATUS

byte (TMD1[31:24]) of the next

descriptor. BUFF is set by the

Am79C973/Am79C975 controller

and cleared by the host.

If a Buffer Error occurs, an Un-

derflow Error will also occur.

BUFF is set by the Am79C973/

Am79C975

controller

and

cleared by the host.

UFLO

Underflow error indicates that the

transmitter has truncated a mes-

sage because it could not read

data from memory fast enough.

UFLO indicates that the FIFO has

emptied before the end of the

frame was reached.

When DXSUFLO (CSR3, bit 6) is

cleared to 0, the transmitter is

turned off when an UFLO error

occurs (CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C973/Am79C975 controller

gracefully

recovers

from

UFLO error. It scans the transmit

descriptor ring until it finds the

start of a new frame and starts a

new transmission.

UFLO is set by the Am79C973/

Am79C975

controller

and

cleared by the host.

EXDEF

Excessive Deferral. Indicates that

the transmitter has experienced

Excessive Deferral on this trans-

mit frame, where Excessive De-

ferral is defined in the ISO 8802-3

(IEEE/ANSI 802.3) standard. Ex-

cessive Deferral will also set the

interrupt bit EXDINT (CSR5, bit

7).

LCOL

Late Collision indicates that a col-

lision has occurred after the first

channel slot time has elapsed.

The Am79C973/Am79C975 con-

troller does not retry on late colli-

sions.

LCOL

set

the

Am79C973/Am79C975 controller

and cleared by the host.

LCAR

Loss of Carrier is set when the

carrier

lost

during

Am79C973/Am79C975 controller

AM79C975VCW Datasheet(PDF) 211 Page - Advanced Micro Devices

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