AP160

Version 0.0

12

AMIC Technology, Inc.

INTERRUPTS

The AP160 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1,

and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be

individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable

bit, EA, which disables all interrupts at once. Note that Table 4 shows that bit position IE.6 is unimplemented. User software

should not write 1s to the bit position, since they may be used in future AMIC products. Timer 2 interrupt is generated by the

logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine

is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in

which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set

at S2P2 and is polled in the same cycle in which the timer overflows.

Table 4: Interrupt Enable (IE) Register

(MSB)

(LSB)

EA

--

ET2

ES

ET1

EX1

ET0

EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol

Position

Function

EA

IE.7

Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA=1, each interrupt

source is individually enabled or disabled by setting or clearing its enable bit.

--

IE.6

Reserved.

ET2

IE.5

Timer 2 interrupt enable bit.

ES

IE.4

Serial Port interrupt enable bit.

ET1

IE.3

Timer 1 interrupt enable bit.

EX1

IE.2

External interrupt 1 enable bit.

ET0

IE.1

Timer 0 interrupt enable bit.

EX0

IE.0

External interrupt 0 enable bit.

User software should never write 1s to unimplemented bits, because they may be used in future AMIC products

INT0

IE0

0

1

TF0

IE1

0

1

INT1

TF1

T1

R1

TF2

EXF2

Figure 6. Interrupt Sources