AP160

Version 0.0

14

AMIC Technology, Inc.

EPROM PROGRAMMING MODE

The setup for programming and verification on-chip OPT EPROM of AP160 is shown in Figure 7 and Figure 8,

independently. The address of the EPROM location to be programmed is applied to ports 1 and 2. The code byte to be

programmed into that location and read verified data are applied to port 0. The programming, verifying, Write Lock bits and

read signature byte mode are selectable by the pins of RST, PSEN, ALE/PROG, P2.6, P2.7, P3.6 and P3.7, as shown in

table 8. The programming and verification waveform is shown in Figure 9. VCC must be rising to VCC1 during

programming.

A0~A7

A8~A12

ADDR

0000H/1FFFH

P1

P2.0~P2.4

P2.6

P2.7

P3.6

P3.7

XTAL2

XTAL1

GND

PSEN

RST

EA

ALE

P0

VCC

VCC1

PGM

DATA

PROG

SEE

TABLE 8.

A0~A7

A8~A12

ADDR

0000H/1FFFH

P1

P2.0~P2.4

P2.6

P2.7

P3.6

P3.7

XTAL2

XTAL1

GND

PSEN

RST

EA

ALE

P0

VCC

VCC1

PGM DATA

(10K PULLUPS)

SEE

TABLE 8.

Figure 7. Programming the EPROM MEMORY

Figure 8. Verifying the EPROM MEMORY.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

Symbol

Parameter

Min.

Max.

Unit

Test Conditions

VPP

Programming Voltage

11.5

12.5

V

VCC1

Programming Supply Voltage

6.0

6.5

V

PP

I

VPP Current During Program

1.0

mA

ALE/PROG =

IL

V

AS

t

Address Valid to Program Low

2

us

DS

t

Input Valid to Program Low

2

us

VPS

t

VPP Setup Time

2

us

VCS

t

VCC Setup Time

2

us

PW

t

Program Pulse Width

95

105

us

DH

t

Data Hold Time

2

us

VR

t

EA/VPP Recovery Time

2

us

DV

t

Data Valid from P2.7

100

ns

DFP

t

Chip Enable to Output Float Delay

130

ns

AH

t

Address Hold Time

0

ns