TLC32046MFKB datasheet(33/56 Pages) TI

33 / 56 page

3–3

3.3.4

Receive Amplifier Input

PARAMETER

TEST

CONDITIONS

MIN

TYP†

MAX

UNIT

A/D converter offset error (filters in)

CMRR

Common-mode rejection ratio at IN+, IN –, or AUX

IN+, AUX IN –

See Note 6

Input resistance at IN+, IN – or

AUX IN+, AUX IN+, AUX IN –, REF

100

Ω

NOTE 6: The test condition is a 0-dBm, 1-kHz input signal with a 16-kHz conversion rate.

3.3.5

Transmit Filter Output

PARAMETER

TEST

CONDITIONS

MIN

TYP†

MAX

UNIT

VOO

Output offset voltage at OUT+ or

OUT (single ended relative to

TLC32046C, I

VOO

OUT– (single-ended relative to

ANLG GND)

TLC32046M

Maximum peak output voltage

swing across RL at OUT+ or OUT

TLC32046C I

RL ≥ 300 Ω,

Offset voltage

±3

VOM

swing across RL at OUT+ or OUT–

(single-ended)

TLC32046C, I

Offset voltage

= 0

±3

VOM

Maximum peak output voltage

swing between OUT+ and OUT–

(differential output)

RL ≥ 600 Ω

±6

† All typical values are at TA = 25°C.

3.3.6

Receive and Transmit Channel System Distortion, SCF Clock

Frequency = 288 kHz (see Note 7)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Attenuation of second harmonic of

Single-ended

A/D input signal

Differential

VI = 0 1 dB to 24 dB

Attenuation of third and higher

Single-ended

VI = – 0.1 dB to – 24 dB

harmonics of A/D input signal

Differential

Attenuation of second harmonic of

Single-ended

D/A input signal

Differential

VI = 0dBto 24 dB

Attenuation of third and higher

Single-ended

VI = – 0 dB to – 24 dB

harmonics of D/A input signal

Differential

† All typical values are at TA = 25°C.

TLC32046MFKB Datasheet(PDF) 33 Page - Texas Instruments

TLC32046MFKB Datasheet(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL