TLC32046MFKB datasheet(23/56 Pages) TI

23 / 56 page

2–9

2.15.2

Primary DX Word Bit Pattern

Using 8-bit processors, the data word is transmitted in the same order as one 16-bit word, but as two bytes

with the two LSBs of the second byte set to zero.

A/D OR D/A MSB

1st bit sent

1st bit sent of 2nd byte

A/D or D/A LSB

↓

↓↓

D15

D14

D13

D12

D11

D10

Table 2–2. Primary DX Serial Communication Protocol

FUNCTIONS

D15 (MSB)-D2

→ DAC Register.

→ TX(A), RA → RX(A) (see Figure 2–1).

→ TX(B), RB → RX(B) (see Figure 2–1).

D15 (MSB)-D2

→ DAC Register.

TA+TA

′ → TX(A), RA+RA′ → RX(A) (see Figure 2–1).

→ TX(B), RB → RX(B) (see Figure 2–1).

The next D/A and A/D conversion period is changed by the addition of TA

′ and RA′ master clock cycles,

in which TA

′ and RA′ can be positive, negative, or zero (refer to Table 2–4).

D15 (MSB)-D2

→ DAC Register.

TA–TA

′ → TX(A), RA–RA′ → RX(A) (see Figure 2–1).

→ TX(B), RB → RX(B) (see Figure 2–1).

The next D/A and A/D conversion period is changed by the subtraction of TA

′ and RA′ master clock cycles,

in which TA

′ and RA′ can be positive, negative, or zero (refer to Table 2–4).

D15 (MSB)-D2

→ DAC Register.

→ TX(A), RA → RX(A) (see Figure 2–1).

→ TX(B), RB → RX(B) (see Figure 2–1).

After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the

desired configuration. In the telephone interface mode, data on DATA DR is routed to DR during

secondary transmission.

NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications)

to the AIC initiates secondary communications upon completion of the primary communications. When the

primary communication is complete, FSX remains high for four SHIFT CLOCK cycles and then goes low and

initiates the secondary communication. The timing specifications for the primary and secondary communications

are identical. In this manner, the secondary communication, if initiated, is interleaved between successive

primary communications. This interleaving prevents the secondary communication from interfering with the

primary communications and DAC timing. This prevents the AIC from skipping a DAC output. FSR is not asserted

during secondary communications activity. However, in the dual-word (telephone interface) mode, FSD is

asserted during secondary communications but not during primary communications.

TLC32046MFKB Datasheet(PDF) 23 Page - Texas Instruments

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