DSP56374 datasheet(17/64 Pages) FREESCALE

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Signal Groupings

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

4.8

Enhanced Serial Audio Interface_1

Table 11. Enhanced Serial Audio Interface_1 Signals

Signal Name

Signal Type

State during

Reset

Signal Description

HCKR_1

Input or output

GPIO

disconnected

High Frequency Clock for Receiver—When programmed as

an input, this signal provides a high frequency clock source

for the ESAI_1 receiver as an alternate to the DSP core

clock. When programmed as an output, this signal can

serve as a high-frequency sample clock (e.g., for external

digital to analog converters [DACs]) or as an additional

system clock.

PE2

Input, output, or

disconnected

Port E2—When the ESAI_1 is configured as GPIO, this

signal is individually programmable as input, output, or

internally disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

HCKT_1

Input or output

GPIO

disconnected

High Frequency Clock for Transmitter—When programmed

as an input, this signal provides a high frequency clock

source for the ESAI_1 transmitter as an alternate to the

DSP core clock. When programmed as an output, this

signal can serve as a high frequency sample clock (e.g., for

external DACs) or as an additional system clock.

PE5

Input, output, or

disconnected

Port E5—When the ESAI_1 is configured as GPIO, this

signal is individually programmable as input, output, or

internally disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

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