IXP2400 datasheet(13/126 Pages) INTEL

13 / 126 page

Intel® IXP2400 Network Processor

Datasheet

2.2.4

Memory Management

The Intel XScale core implements the Memory Management Unit (MMU) Architecture specified

in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to

physical address translation. The MMU Architecture also specifies the caching policies for the

instruction cache and data memory. These policies are specified as page attributes and include:

• Identifying code as cacheable or non-cacheable

• Selecting between the mini-data cache or data cache

• Write-back or write-through data caching

• Enabling data write allocation policy

• Enabling the write buffer to coalesce stores to external memory

2.2.5

Branch Target Buffer

The Intel XScale core provides a Branch Target Buffer (BTB) to predict the outcome of

branch-type instructions. It provides storage for the target address of branch-type instructions and

predicts the next address to present to the instruction cache when the current instruction address is

that of a branch. The BTB holds 128 entries.

2.3

Microengines

The Microengines (MEs) do most of the programmable per-packet processing in the IXP2400.

There are eight MEs, connected as shown in Figure 4. The MEs have access to all shared resources

(SRAM, DRAM, MSF, etc.) as well as private connections between adjacent MEs.

The MEs provide support for software-controlled multi-threaded operation. Given the disparity in

processor cycle times versus external memory times, a single thread of execution will often block,

waiting for external memory operations to complete. Having multiple threads available allows for

threads to interleave operation; there is often at least one thread ready to run while others are

blocked.

IXP2400 Datasheet(PDF) 13 Page - Intel Corporation