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IXP2400 Datasheet(PDF) 4 Page - Intel Corporation

Part # IXP2400
Description  Intel짰 IXP2400 Network Processor
PDF  126 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

IXP2400 Datasheet(HTML) 4 Page - Intel Corporation

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Intel® IXP2400 Network Processor
4
Datasheet
3.3.3
SlowPort Clock Behavior During Reset................................................. 69
3.3.4
Pullup/Pulldown and Unused Pin Guidelines ........................................ 69
3.4
Ball Information .................................................................................................. 70
3.5
Ball List Tables................................................................................................... 72
3.5.1
Balls Listed in Alphanumeric Order by Signal Name............................. 72
3.5.2
Balls Listed in Alphanumeric Order by Ball Location............................. 85
4.0
Electrical Specifications .................................................................................................. 98
4.1
Absolute Maximum Ratings ............................................................................... 98
4.1.1
Reducing Power Consumption............................................................ 100
4.2
AC/DC Specifications....................................................................................... 101
4.2.1
Clock Timing Specifications ................................................................ 101
4.2.2
PCI I/O Unit ......................................................................................... 101
4.2.3
SRAM .................................................................................................. 105
4.2.4
DDR SDRAM ...................................................................................... 107
4.2.5
Media and Switch Fabric (MSF) Interface ........................................... 114
4.2.6
CBus ................................................................................................... 117
4.2.7
SlowPort, GPIO, and Serial I/O Buffer ................................................ 118
4.2.8
JTAG ................................................................................................... 121
5.0
Mechanical Specifications............................................................................................. 124
5.1
Package Dimensions ....................................................................................... 124
Figures
1
IXP2400 Network Processor OC-48 Line Card ...................................................7
2
IXP2400 Network Processor Functional Signal Groups Diagram 1 ....................8
3
IXP2400 Network Processor Functional Signal Groups Diagram 2 ....................9
4
IXP2400 Network Processor Chassis Concept Block Diagram ........................10
5
Intel XScale® Core Internal Block Diagram .......................................................12
6
Microengine Block Diagram ..............................................................................14
7
Clock Configuration...........................................................................................18
8
Example SlowPort Connection..........................................................................22
9
High-Level Overview of Ballout
Functional Groupings Diagram (Ball Side) ........................................................23
10
IXP2400 Network Processor Ball Map (bottom left side) ..................................70
11
IXP2400 Network Processor Ball Map (bottom right side) ................................71
12
PLL Power Supply Connection .......................................................................100
13
SYS_CLK Timing ............................................................................................101
14
PCI Clock Signal AC Parameter Measurements.............................................103
15
PCI Bus Signals ..............................................................................................104
16
QDR Load Circuit ............................................................................................106
17
QDRII Timing Reference .................................................................................107
18
Data and Error Correction Setup/Hold Relationship to/from
Data Strobe (Read Operation) ........................................................................109
19
Data and Error Correction Valid Before and After Data
Strobe (Write Operation) .................................................................................110
20
Write Preamble Duration .................................................................................110
21
Write Postamble Duration ...............................................................................110
22
Command Signals Valid Before and After Clock Rising Edge ........................110
23
Clock Enable Valid Before and After Clock Rising Edge ................................111



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