IXP2400 datasheet(18/126 Pages) INTEL

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Intel® IXP2400 Network Processor

Datasheet

• Samsung* 36-Mb QDRII x9 K7R320982M-FC20 or 36-Mb QDRII x18 K7R321882M-FC20

SRAM

• IDT* IDT71T6280H 9-Mb pipelined QDR SRAM burst of 2 (512K x 18)

• Cypress* CY7C1302V25 9-Mb pipelined SRAM with QDR architecture (512K x 18)

Each of the two QDR ports are QDR- and QDRII-compatible. Each port implements the “_K” and

“_C” output clocks as an input and their inversions. The “_C” clocks are used for reading SRAM

data and the “_K” clocks are used for writing SRAM data. Extensive work has been performed to

control the impedance within the IXP2400 for IXP2400-initiated signals that drive QDR parts. The

receivers of IXP2400 QDR have on-die termination.

The IXP2400 IO driver/receiver can drive up to four QDR device loads. The IXP2400 supports

bursts of two SRAM devices. The IXP2400 uses one pair of the Cn/Cn# clocks for read data; the

other pair is terminated on the die.

The SRAM controller can also be configured to interface to an external coprocessor that adheres to

the QDR electricals and protocol.

2.5.1

SRAM Controller Configurations

Each channel has enough address pins (24) to support up to 64 MB of SRAM. The SRAM

controllers can directly generate multiple port enables (up to four pairs) to allow for depth

expansion. Two pairs of pins are dedicated for port enables. Smaller RAMs use fewer address

Figure 7. Clock Configuration

B0059-01

Clam-shelled SRAMs

C/C#

Package Balls

Termination

Intel®

IXP2400

Network

Processor

C1n/C1n#

K1/K1#

K/K#

C/C#

C1/C1#

K2/K2#

C2/C2#

C1/C1#

C2/C2#

C2n/C2n#

Termination

Vtt

Ω

Note: Leave CQ/CQ# as NC.

Vtt

IXP2400 Datasheet(PDF) 18 Page - Intel Corporation

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