EP2C8 datasheet(55/168 Pages) ALTERA

55 / 168 page

Altera Corporation

2–43

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration

The Cyclone II device IOE includes programmable delays to ensure zero

hold times, minimize setup times, or increase clock to output times.

A path in which a pin directly drives a register may require a

programmable delay to ensure zero hold time, whereas a path in which a

pin drives a register through combinational logic may not require the

delay. Programmable delays decrease input-pin-to-logic-array and IOE

input register delays. The Quartus II Compiler can program these delays

to automatically minimize setup time while providing a zero hold time.

Chip-Wide Reset

OE Register

VCCIO

Optional

PCI Clamp

Column

or Row

Interconect

io_clk[5..0]

Input Register

Input Pin to

Input Register Delay

or Input Pin to

Logic Array Delay

Open-Drain Output

sclr/preset

clkout

ce_out

aclr/prn

clkin

ce_in

Output

Pin Delay

Programmable

Pull-Up

Resistor

Bus Hold

PRN

CLRN

Output Register

PRN

CLRN

PRN

CLRN

VCCIO

data_in0

data_in1

ENA

EP2C8 Datasheet(PDF) 55 Page - Altera Corporation

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