LP38851 datasheet(14/29 Pages) TI

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LP38851

SNVS492C – JUNE 2007 – REVISED APRIL 2013

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Please refer to Application Note AN-1378 (SNVA112) for additional information on how resistor tolerances affect

the calculated VOUT value.

INPUT VOLTAGE

The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage,

which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is

used for VBIAS.

For applications where VBIAS is higher than 4.5V, VIN must be no greater than 4.5V, otherwise output voltage

accuracy may be affected.

BIAS VOLTAGE

The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide

gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the

operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V , VBIAS must be between 4.5V and 5.5V to

ensure proper operation of the device.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is

below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.

As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is

approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.

When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the

device will be functional, but the operating parameters will not be within the specified limits.

SUPPLY SEQUENCING

There is no requirement for the order that VIN or VBIAS are applied or removed.

One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO

threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point

the benefits of Soft-Start will be compromised.

In any case, the output voltage cannot be specified until both VIN and VBIAS are within the range of specified

operating values.

If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin

must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.

REVERSE VOLTAGE

A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.

Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that

the input to output voltage becomes reversed.

The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass

element is not driven, there will not be any reverse current flow through the pass element during a reverse

voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the

Enable pin is held low.

When VBIAS is above the UVLO threshold, and the Enable pin is above the VEN(ON) threshold, the control circuitry

is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the

control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to

fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of

the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this

manner will not damage the device as the current will rapidly decay. However, continuous reverse current should

be avoided.

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