8

TS68302

2117A–HIREL–11/02

This device contains protective circuitry to protect the inputs against damage due to high

static voltages or electrical fields; however, it is advised that normal precautions be

taken to avoid application of any voltages higher than maximum-rated voltages to this

high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to

an appropriate logic voltage level (e.g., either GND or V

Figure 5. Clock Input Timing Diagram

Note:

Timing measurements are referenced to and from a low voltage of 0.8V and a voltage of 2.0V, unless otherwise noted. The volt-

age swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between

0.8V and 2.0V.

Power Considerations

(1)

θ

Note:

For T

For most applications P

An approximate relationship between P

P

(2)

Solving equations (1) and (2) for K gives:

K = P

(3)

where K is a constant pertaining to the particular part. K can be determined from equa-

tion (3) by measuring P

values of P

value of T

2.0V

0.8V

tr (C)

tf (C)

tcyc

Table 4. Thermal Characteristics at 25°C

Package

Symbol

Parameter

Value

Unit

PGA 132

θ

JA

θ

JC

Thermal Resistance - Ceramic Junction To Ambient

Thermal Resistance - Ceramic Junction To Case

33

5

°C/W

°C/W

CERQUAD 132

θ

JA

θ

JC

Thermal Resistance - Ceramic Junction To Ambient

Thermal Resistance - Ceramic Junction To Case

46

2

°C/W

°C/W