TS68302VR1BSLASHT16 datasheet(39/47 Pages) ATMEL

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TS68302

2117A–HIREL–11/02

Main Controller

The main controller is a microcode RISC processor that services all the serial channels.

The main controller transfers data between the serial channels and internal/external

RAM, executes host commands, and generates interrupts to the interrupt controller.

Data is transferred from the serial channel to the dual-port RAM or to the external mem-

ory through the peripheral bus. If data is transferred between the SCC channels and

external memory, the main controller uses up to six serial DMA channels for the trans-

fer. The main controller also controls all character and address comparison and cyclic

redundancy check (CRD) generation and checking.

The execution unit includes the arithmetic logic unit (ALU), which performs arithmetic

and logic operations on the registers.

Serial Communication

Controllers

The TS68302 has three independent SCCs. Each SCC can be configured to implement

different protocols - for example, to perform a gateway function or to interface to an

ISDN basic rate channel. To simplify programming, each protocol implementation uses

identical data structures.

Five protocols are supported: high-level data link control (HDLC), binary synchronous

communication (BISYNC), synchronous/asynchronous digital data communications

message protocol (DDCMP), V.110, universal asynchronous receiver transmitter

(UART), and a fully transparent mode. To aid system diagnostics, each SCC may be

configured to operate in either an echo or loopback mode. In echo mode, the IMP

retransmits any signals received; in loopback mode, the IMP locally receives signals

originating from itself.

The clock pins (RCLK, TCLK) for each SCC can be programmed for either an external

or internal source, with user-programmable baud rates available for each SCC channel.

Each SCC also supports the standard modem control signals: request to send (RTS),

clear to send (CTS), and carrier detect (CD). Other modem signals may be provided

through the parallel I/O pins.

The SCC features are as follows:

•

programmable baud rate generator driven by the internal or external clock,

•

data may be clocked by the programmable baud rate generator or directly by an

external clock,

•

provides modem signals RTS, CTS, and CD,

•

Full-duplex operation,

•

Automatic echo mode,

•

Local loopback mode,

•

Baud rate generator outputs available externally.

The SCC HDLC mode key features are as follows:

•

flexible data buffers with multiple buffers per frame allowed,

•

separate interrupts for frames and buffers (receive and transmit),

•

four address comparison registers with mask,

•

maintenance of five 16-bit counters,

•

flag/abort/idle generation/detection,

•

zero insertion/deletion,

•

NRZ/NRZI data encoding,

•

16-bit or 32-bit CRC-CCITT generation/checking,

•

detection of non-octet aligned frames,

TS68302VR1B/T16 Datasheet(PDF) 39 Page - ATMEL Corporation

TS68302VR1B/T16 Datasheet(HTML) 39 Page - ATMEL Corporation

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