14

TS68302

2117A–HIREL–11/02

Notes:

1. For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum columns.

2. Actual value depends on clock period.

3. When AS and R/W are equally loaded (±20%), subtract 5 ns from the values given in these columns.

4. If the asynchronous input setup (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)

requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.

5. The TS68302 will negate BG and begin driving the bus if external arbitration logic negates BR before asserting BGACK.

6. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.

7. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a synchronous input

using the asynchronous input setup time (#47).

8. For power-up, the TS68302 must be held in the reset state for 100 ms to allow stabilization of on-chip circuit. After the sys-

tem is powered up #56 refers to the minimum pulse width required to reset the processor.

9. Occurs on S0 of SDMA read/write access when the SDMA becomes bus master.

10. This specification is valid only when the RMCST bit is set in the SCR register.

44

AS, DS negated to AVEC negated

0

50

ns

46

t

GAL

BGACK width low

1.5

clks

47

t

ASI

Asynchronous input setup time

(4)

10

ns

48

BERR asserted to DTACK asserted

(2)(7)

10

ns

53

t

CHDOI

Data-out hold from clock high

0

ns

55

t

RLDBD

R/W asserted to data bus impedance change

0

ns

56

HALT/RESET pulse width

(8)

10

clks

57

t

GASD

BGACK negated to AS, DS, R/W driven

1.5

clks

57A

t

GAFD

BGACK negated to FC

1

clks

58

BR negated to AS, DS, R/W driven

(5)

1.5

clks

58A

t

RHFD

BR negated to FC

(5)

1clks

60

t

CHBCL

Clock high to BCLR asserted

30

ns

61

Clock high to BCLR negated

(9)

30

ns

62

t

CLRML

Clock low (S0 falling edge during read) to RMC asserted

30

ns

63

t

CHRMH

Clock high (S7 rising edge during write) to RMC negated

30

ns

64

RMC negated to BG asserted

(10)

30

ns

Table 8. AC Electrical Specifications

IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz (Continued)

Num.

Symbol

Parameter

Min

Max

Unit