TS68302VR1BSLASHT16 datasheet(13/47 Pages) ATMEL

13 / 47 page

TS68302

2117A–HIREL–11/02

Table 8. AC Electrical Specifications

IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz

Num.

Symbol

Parameter

Min

Max

Unit

CHFCADV

Clock high to FC, address valid

7tCHADZ

Clock high to address, data bus high impedance (maximum)

CHAFI

Clock high to address, FC invalid (minimum)

CHSL

Clock high to AS, DS asserted

(1)

330

AFCVSL

Address, FC valid to AS, DS asserted (read)/AS asserted

(write)

(2)

CLSH

Clock low to AS, DS negated

(1)

tSHAFI

AS, DS negated to address, FC invalid

(2)

AS (and DS read) width asserted

(2)

120

14A

DSL

DS width asserted, write

(2)

tSH

AS, DS width negated

(2)

CHCZ

Clock high to control bus high impedance

SHRH

AS, DS negated to R/W invalid

(2)

tCHRH

Clock high to R/W high

(1)

CHRL

Clock high to R/W low

(1)

20A

ASRV

AS asserted to R/W low (write)

(2)(3)

tAFCVRL

Address FC valid to R/W low (write)

(2)

RLSL

R/W low to DS asserted (write)

(2)

CLDO

Clock low to data-out valid

tSHDOI

AS, DS, negated to data-out invalid (write)

(2)

DOSL

Data-out valid to DS asserted (write)

(2)

DICL

Data-in valid to clock low (Setup time on read)

(4)

7ns

tSHDAH

AS, DS negated to DTACK negated (asynchronous hold)

(2)

110

SHDII

AS, DS negated to data-in invalid (hold time on read)

SHBEH

AS, DS negated to BEER negated

tDALDI

DTACK asserted to data-in valid (setup time)

(2)(4)

RHr, tRHf

HALT and RESET input transition time

150

CHGL

Clock high to BG asserted

tCHGH

Clock high to BG negated

BRLGL

BR asserted to BG asserted

2.5

4.5

clks

BRHGH

BR negated to BG negated

(5)

1.5

2.5

clks

tGALGH

BGACK asserted to BG negated

2.5

4.5

clks

37A

GALBRH

BGACK asserted to BG negated

(6)

1.5

ns/clks

GLZ

BG asserted to control, address, data bus high impedance

(AS negated)

BG width negated

1.5

clks

TS68302VR1B/T16 Datasheet(PDF) 13 Page - ATMEL Corporation

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