TS68302VR1BSLASHT16 datasheet(31/47 Pages) ATMEL

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TS68302

2117A–HIREL–11/02

Figure 24. GSI Timing Diagram

Notes:

1. The ratio CLK/TCLK1 must be greater than 2.5/1.

2. L1T x D becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used.

3. Specification valid for both sync methods.

4. See Figure 25.

Table 21. AC Electrical Specifications - PCM Timing(4) f = 16.67 MHz

There are two sync types:

Short frame - Sync signals are one clock cycle prior to the data.

Long frame - Sync signals are N-bits that envelope the data, N > 0.

Num.

Parameter

Min

Max

Unit

300

L1CLK (PCM clock) frequency

(1)

6.66

MHz

301

L1CLK width low/high

302

L1SY0-L1SY1 setup time to L1CLK falling edge

303

L1SY0-L1SY1 hold time from L1CLK falling edge

304

L1SY0-L1SY1 width low

L1CLK

305

Time between successive sync signals (short frame)

L1CLK

306

L1T x D data valid after L1CLK rising edge

(2)

070

307

L1T x D to high impedance (from L1CLK rising edge)

308

L1R x D setup time (to L1CLK falling edge)

(3)

309

L1R x D hold time (from L1CLK falling edge)

(3)

310

L1T x D data valid after syncs rising edge (long)

(2)

100

311

L1T x D to high impedance (from L1SY0-L1SY1 falling edge) (long)

TS68302VR1B/T16 Datasheet(PDF) 31 Page - ATMEL Corporation

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